Scalable Architecture for Dual Basis Multiplication over GF ( 2 m )

A novel low-complexity scalable and systolic dual basis multiplier over GF(2 ) m is proposed in this paper. It is derived by utilizing the block Hankel matrixvector representation and is suitable for finite fields generated by irreducible trinomials. The proposed scalable architecture can achieve good trade-off between throughout performance and hardware complexity for implementing cryptographic schemes in a constrained environment such as embedded systems by choosing appropriate digit size d. Analytical results reveal that the proposed scalable architecture has lower space complexity as compared to non-scalable architectures. Furthermore, the proposed architecture has the features of regularity, modularity and concurrency, and is well suitable for VLSI implementations.